1. Field of the Invention
The present invention relates to a voltage boosting circuit for generating a voltage higher than the power-supply voltage in, for example, a semiconductor memory device.
2. Description of the Related Art
Voltage boosting circuits are used in various types of semiconductor devices. As one example, voltage boosting circuits are used in dynamic random-access memory (DRAM) devices to generate a potential exceeding the power-supply potential by at least the threshold voltage of the transistors in the memory-cell array. This boosted potential is useful for writing data into the memory cells.
A conventional voltage boosting circuit of the type used in a DRAM comprises a pair of charge pumps coupled to an output node. One charge pump, which is capable of supplying only a relatively small amount of current, is activated whenever the output node potential falls below the required level; this charge pump is used primarily to compensate for the small amount of current leakage that occurs during standby periods. The other charge pump, which can supply more current, is activated if the output node potential falls below the required level during active periods, while the memory cells are being accessed.
One disadvantage of this conventional voltage boosting circuit is that the potential of the output node at the start of a memory access operation varies, depending on, for example, the elapsed time since the preceding memory access operation, the duration of the previous memory access operation, and the rate at which current was consumed during that memory access operation. As a result, voltage boosting tends to occur at unpredictable times during the memory access operation and can cause electrical noise problems. In addition, for some combinations of the above factors, the charge-pump operation becomes unstable, and the output node potential deviates greatly from the desired potential.
This stability problem is aggravated if there is a long delay in detecting the potential level of the output node. The severity of the problem could be reduced by shortening the detection delay, by detecting the potential at more frequent intervals, for example, but the circuit that detects the output node potential consumes power in doing so, so this solution would have the undesired consequence of increasing the total power dissipation of the device.
Further information about the above problems, which are not limited to memory circuits, will be given in the detailed description of the invention.
An object of the present invention is to improve the stability of operation of a voltage boosting circuit.
Another object of the invention is to reduce electrical noise.
The invented voltage boosting circuit receives power at a power-supply potential and supplies current from an output node to a load circuit. The voltage boosting circuit includes a first charge pump that boosts the output node to a potential exceeding the power-supply potential when the load circuit becomes active, as indicated by a control signal. The voltage boosting circuit also includes a second charge pump that boosts the output node to a potential exceeding the power-supply potential if the potential of the output node goes below a predetermined level while the load circuit is active, as indicated by the control signal and an activation signal. The voltage boosting circuit further includes a voltage detector that detects the potential of the output node and generates the activation signal.
The first charge pump improves the stability of the voltage boosting circuit by ensuring that the output node is always boosted to an adequate potential when the load circuit becomes active. This reduces the need for charge pumping during the ensuing period while the load circuit is active, so less electrical noise is generated while the load circuit is operating.
The activation signal may be synchronized with the control signal so that the second charge pump operates only if the output node potential is below the predetermined level when the load circuit becomes active, to further reduce electrical noise while the load circuit is operating.
In this case, the operation of the second charge pump may be delayed by a fixed interval from the operation of the first embodiment, reducing electrical noise by ensuring that the two charge pumps do not operate simultaneously.
The first charge pump may have a switchable current-supplying capability, which can be selected according to the requirements of the load circuit to avoid unnecessary boosting of the potential of the output node.